1. Field of the Invention
The present invention relates generally to clocking circuits. More particularly, the present invention relates to a clocking circuit that maintains clock accuracy at power down.
2. Discussion of the Related Art
In various electrical devices, reference clock signals are needed to clock digital circuits inside integrated circuits. One example of this type of circuit is in a motor controller that is used to control, for example, a hard disk drive. In such a motor controller, when the power supply is providing power to the controller, a reference clock is typically available to the integrated circuit from an external reference clock generator, such as a quartz oscillator based clock. However, once the power to the hard disk drive and associated control circuitry is shut off, as during power down, the motor controller is required to continue to operate in order to properly protect, for example, the actuator of the hard disk drive. In order for the motor controller to continue operating properly, certain timer circuits need to accurately maintain their operation during the power down sequence. To provide the energy necessary to operate the motor controller and associated timer circuits during the power down sequence, the back EMF of the spinning hard disk drive motor may be rectified. Although this provides power to the motor controller, since the main power supply is no longer operating, the reference clock generator is not operative and therefore the clock signal needed to operate the timer circuits has to be obtained in another way.
Conventionally, R/C (Resistor/capacitor) oscillators are used to provide a clock signal during the power down sequence. However, more stringent requirements on the accuracy of the clock frequency required by modem circuits would require complex trimming and thermal calibration. The added expense associated with trimming and calibration makes this solution undesirable.
Another alternative would be to provide an additional quartz oscillator powered by the rectified energy of the spinning motor. However, this solution would add additional expense that would be considered undesirable in certain applications.
Therefore, an object of the present invention is to provide a method and apparatus that overcomes at least these problems.
The present invention overcomes at least the foregoing problems by providing a circuit that synchronizes an output clock signal to a second clock signal, the circuit including a frequency locked loop that receives the output clock signal and the second clock signal, modifies a frequency of the output clock signal in response to a difference in frequency between the output clock signal and the second clock signal to provide an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal and wherein the frequency locked loop continues to provide the output clock signal in the absence of the second clock signal. During a power down sequence, the frequency of the output clock signal does not vary, but remains at the frequency last locked to by the frequency locked loop.
According to one embodiment of the invention, the second clock signal is provided by a quartz crystal oscillator.
According to one embodiment of the invention, a first clock signal is provided by a resistor/capacitor oscillator circuit.
According to another embodiment of the invention, the frequency locked loop circuit includes a frequency discriminator and a controlled signal generator.
According to another embodiment of the invention, the frequency discriminator compares the frequency of the second clock signal with the frequency of the output clock signal and provides a signal indicative of the difference between the frequency of the second clock signal and the frequency of the output clock signal.
According to another embodiment of the invention, the controlled signal generator responds to the frequency discriminator to increase the frequency of the output clock signal if the frequency of the second clock signal is greater than the frequency of the output clock signal.
According to another embodiment of the invention, the controlled signal generator responds to the frequency discriminator to decrease the frequency of the output clock signal if the frequency of the second clock signal is less than the frequency of the output clock signal.
According to another embodiment of the invention, the controlled signal generator includes at least one counter.
According to another embodiment of the invention, the at least one counter includes a down counter and a saturated up/down counter.
According to an embodiment of the invention, the at least one counter includes a counter and an up/down counter.
According to another embodiment of the invention, the predetermined error band is less than or equal to one percent of the frequency of the second clock signal.
According to another embodiment of the invention, the circuit is incorporated into a motor controller for a hard disk drive.
According to another embodiment of the invention, the quartz crystal oscillator is powered by a first power supply and wherein the frequency locked loop continues to provide the output clock signal when the first power supply no longer operates.
According to another embodiment of the invention, a method of synchronizing an output clock signal to a second clock signal is provided, the method comprising the steps of receiving an output clock signal, receiving a second clock signal, comparing a frequency of the second clock signal to a frequency of the output clock signal, modifying a frequency of the output clock signal in response to the comparing step and providing an output clock signal having a frequency within a predetermined error band of the frequency of the second clock signal, and continuing to provide the output clock signal in the absence of the second clock signal.
According to another embodiment, the method further comprises the step of increasing the frequency of the output clock signal if the frequency of the second clock signal is greater than the frequency of the output clock signal.
According to another embodiment of the invention, the method further comprises the step of decreasing the frequency of the output clock signal if the frequency of the second clock signal is less than the frequency of the output clock signal.